Clock skew between multiple clock domains on the same die can be reduced using phase locked loops (PLLs) and skew compensators with delay lines. However, to reduce large clock skews (e.g., delay mismatch of 10's or 100's of picoseconds on typical CPU clock trees that might be operating at a few GHz frequency), the skew compensator itself can introduce several hundred picoseconds of delay which may introduce additional clock skew variation and supply noise induced jitter.
Multi-chip packaging (MCP) is used to consolidate multiple dies on a single package. To reduce clock skew between multiple dies, asynchronous clocking techniques may be used. Such techniques rely on pipelines such as first-in-first-out (FIFO) pipelines. For example, FIFO pipelines are used on clock domains on either side of the links between multiple dies. To cope with large clock skews, however, deeper (i.e., longer) FIFO pipeline depth is used which increases latency. An increase in latency reduces overall performance of the processor.
Delay matching techniques using delay-line based skew compensators, techniques used for skew reduction on a single die, are not suited for use in MCP because aligning clock edges at clock distribution ends of multiple clock domains on different dies is complicated and perhaps not feasible. The issues of traditional clock skew compensation discussed above with reference to MCPs are also applicable to three dimensional (3D) integrated circuit (IC) stacked dies.